- All sections
- G - Physics
- G06F - Electric digital data processing
- G06F 7/507 - Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
Patent holdings for IPC class G06F 7/507
Total number of patents in this class: 40
10-year publication summary
|
0
|
11
|
0
|
2
|
13
|
1
|
5
|
1
|
5
|
1
|
| 2015 | 2016 | 2017 | 2018 | 2019 | 2020 | 2021 | 2022 | 2023 | 2024 |
Principal owners for this class
| Owner |
All patents
|
This class
|
|---|---|---|
| ARM Limited | 4353 |
8 |
| Cambricon Technologies Corporation Limited | 302 |
8 |
| Board of Regents, The University of Texas System | 5370 |
7 |
| Samsung Electronics Co., Ltd. | 131630 |
2 |
| Micron Technology, Inc. | 24960 |
2 |
| Texas Instruments Incorporated | 19376 |
2 |
| Intel Corporation | 45621 |
1 |
| Fujitsu Limited | 19265 |
1 |
| Olympus Corporation | 13667 |
1 |
| Altera Corporation | 2241 |
1 |
| FlashSilicon Incorporation | 24 |
1 |
| Ningbo University | 37 |
1 |
| OmniVision Technologies, Inc. | 1502 |
1 |
| NXP USA, Inc. | 4155 |
1 |
| Marvell Asia PTE, Ltd. | 6841 |
1 |
| Cavium International | 5549 |
1 |
| Lemon Inc. | 936 |
1 |
| Other owners | 0 |